Designing of 2-Stage CPU Scheduler Using Vague Logic

TitleDesigning of 2-Stage CPU Scheduler Using Vague Logic
Publication TypeJournal Article
Year of PublicationSubmitted
Subsidiary AuthorsAburas, A
JournalAdvances in Fuzzy Systems
Pagination10
Date Published07/2014
Type of ArticleResearch
Other Numbershttp://dx.doi.org/10.1155/2014/841976
URLhttp://www.hindawi.com/journals/afs/2014/841976
Refereed DesignationDoes Not Apply