CS303 Digital Design
CS303 Digital Design
Syllabus | International University of Sarajevo - Last Update on Sep 09, 2025
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Computer Sciences and Engineering
Mohammad Al Samman
Course Lecturer
Course Objectives
To introduce the main building blocks of digital circuits and develop the skills of the students in the area of logic design and digital systems
Learning Outcomes
After successful completion of the course, the student will be able to:
Course Materials
Required Textbook
R1: Digital Design, Morris M. Mano, Michael D. Ciletti, Pearson (5th Ed.) R2: Fundamentals of digital logic with VHDL design, Stephen Brown, Zvonko Vranesic, McGraw Hill (3rd Ed.)
Additional Literature
1. Digital Design Using VHDL A System Approach, William J. Dally, R. Curtis Harting, Tor M. Aamodt, Cambridge University Press, 2015 2. Digital Design and Computer Architecture, David Harris and Sarah Harris, Elsevir, 2013Teaching Methods
Class discussions with examples
Active tutorial sessions for engaged learning and continuous feedback on progress
Assignments and laboratory exercises that involve work with commercial programmable logic circuits
Weekly Topics
| Week | Topic | Readings / References |
|---|---|---|
| 1 | Introduction | R1: Ch1 |
| 2 | Introduction, Digital Systems and Binary Numbers | R1: Ch1 |
| 3 | Boolean Algebra and Logic Gates | R1: Ch2 |
| 4 | Gate-Level Minimization | R1: Ch3 |
| 5 | Gate-Level Minimization | R1: Ch3 |
| 6 | Combinational Logic | R1: Ch4 |
| 7 | Combinational Logic | R1: Ch4 |
| 8 | MIDTERM EXAM | -- |
| 9 | Combinational Logic | R1: Ch4 |
| 10 | Synchronous Sequential Logic | R1: Ch5 |
| 11 | Synchronous Sequential Logic | R1: Ch5 |
| 12 | Synchronous Sequential Logic | R1: Ch5 |
| 13 | Registers and Counters | R1: Ch6 |
| 14 | Registers and Counters | R1: Ch6 |
| 15 | General Revision | -- |
Course Schedule (All Sections)
| Section | Type | Day 1 | Venue 1 | Day 2 | Venue 2 |
|---|---|---|---|---|---|
| CS303.1 | Course | Wednesday 13:00 - 15:50 | B F2.15 - Amphitheater II | - | - |
| CS303.2 | Tutorial | Friday 09:00 - 10:50 | A B.2 - EE Lab | - | - |
| CS303.3 | Tutorial | Thursday 17:00 - 18:50 | A F2.14 - Amphitheater II | - | - |
| CS303.1 | Tutorial | Thursday 09:00 - 10:50 | A B.2 - EE Lab | - | - |
Office Hours & Room
| Day | Time | Office | Notes |
|---|---|---|---|
| Tuesday | 15:00 - 16:00 | A F2.7 | |
| Wednesday | 13:00 - 15:00 | A F2.7 | |
| Thursday | 11:00 - 13:00 | A F2.7 |
Assessment Methods and Criteria
Assessment Components
Final Exam
AI: Not AllowedAlignment with Learning Outcomes : 1 2 4
Laboratory/Simulation Assignments
AI: Not AllowedAlignment with Learning Outcomes : 3 5
Quizzes
AI: Not AllowedAlignment with Learning Outcomes : 1 2 4
Midterm exam
AI: Not AllowedAlignment with Learning Outcomes : 1 2 4
IUS Grading System
| Grading Scale | IUS Grading System | IUS Coeff. | Letter (B&H) | Numerical (B&H) |
|---|---|---|---|---|
| 0 - 44 | F | 0 | F | 5 |
| 45 - 54 | E | 1 | ||
| 55 - 64 | C | 2 | E | 6 |
| 65 - 69 | C+ | 2.3 | D | 7 |
| 70 -74 | B- | 2.7 | ||
| 75 - 79 | B | 3 | C | 8 |
| 80 - 84 | B+ | 3.3 | ||
| 85 - 94 | A- | 3.7 | B | 9 |
| 95 - 100 | A | 4 | A | 10 |
Late Work Policy
Information about late submission policies will be shared during class and posted in this section. Please check back for official guidelines.
ECTS Credit Calculation
📚 Student Workload
This 6 ECTS credit course corresponds to 150 hours of total student workload, distributed as follows:
Lecture Hours
42 hours ⏳ (14 week × 3 h)
Assignments
10 hours ⏳ (10 week × 1 h)
Lab & Reporting
20 hours ⏳ (10 week × 2 h)
Home Study
13 hours ⏳ (13 week × 1 h)
In-term Exam Study
15 hours ⏳ (1 week × 15 h)
Final Exam Study
30 hours ⏳ (2 week × 15 h)
Project
20 hours ⏳ (5 week × 4 h)
150 Total Workload Hours
6 ECTS Credits
Course Policies
Academic Integrity
All work submitted must be your own. Plagiarism, cheating, or any form of academic dishonesty will result in disciplinary action according to university policies. When in doubt about citation practices, consult the instructor.
Attendance Policy
Students are expected to adhere to the attendance requirements as outlined in the International University of Sarajevo Study Rules and Regulations. Excessive absences, whether excused or unexcused, may impact academic performance and eligibility for assessment. Mandatory sessions (e.g., labs, workshops) require attendance unless formally exempted. For detailed policies on absences, documentation, and penalties, please refer to the official university regulations.
Technology & AI Policy
Laptops/tablets may be used for note-taking only during lectures. Phones should be silenced and put away during all class sessions. Audio/video recording requires prior permission from the instructor.
Artificial Intelligence (AI) Usage: The use of AI tools (e.g., ChatGPT, Copilot, Gemini) varies by assessment component. Please refer to the AI usage indicator next to each assessment item in the Assessment Methods and Criteria section above. Submitting AI-generated content as your own work, where AI is not explicitly allowed, constitutes an academic integrity violation.
Communication Policy
All course-related communication should occur through official university channels (institutional email or SIS). Emails should include [CS303] in the subject line.
Academic Quality Assurance Policy
Course Academic Quality Assurance is achieved through Semester Student Survey. At the end of each academic year, the institution of higher education is obliged to evaluate work of the academic staff, or the success of realization of the curricula.
Learning Tips
Be prepared to contribute thoughtfully during class discussions, labs, or collaborative work. Active participation deepens understanding and encourages critical thinking.
Complete assigned readings or prep materials before class. Take notes, highlight key ideas, and jot down questions. Aim to grasp core concepts and their applications—not just facts.
Use course frameworks or methodologies to analyze problems, case studies, or projects. Begin early to allow time for reflection and refinement. Seek feedback to improve your work.
Don’t hesitate to reach out when something is unclear. Use office hours, discussion boards, or peer networks to clarify concepts and stay on track.
Syllabus Last Updated on Sep 09, 2025 | International University of Sarajevo
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Referencing Curricula Print this page
| Course Code | Course Title | Weekly Hours* | ECTS | Weekly Class Schedule | ||||||
| T | P | |||||||||
| CS303 | Digital Design | 3 | 2 | 6 | Wed. 13:00 to 16:00 | |||||
| Prerequisite | None | It is a prerequisite to | CS309, EE435, EE436 | |||||||
| Lecturer | Mohammad Al Samman | Office Hours / Room / Phone | Tuesday: 15:00-16:00 Wednesday: 13:00-15:00 Thursday: 11:00-13:00 |
|||||||
| malsamman@ius.edu.ba | ||||||||||
| Assistant | Mr. Kefah Fattash | Assistant E-mail | kfattash@ius.edu.ba | |||||||
| Course Objectives | To introduce the main building blocks of digital circuits and develop the skills of the students in the area of logic design and digital systems | |||||||||
| Textbook | R1: Digital Design, Morris M. Mano, Michael D. Ciletti, Pearson (5th Ed.) R2: Fundamentals of digital logic with VHDL design, Stephen Brown, Zvonko Vranesic, McGraw Hill (3rd Ed.) | |||||||||
| Additional Literature |
|
|||||||||
| Learning Outcomes | After successful completion of the course, the student will be able to: | |||||||||
|
||||||||||
| Teaching Methods | Class discussions with examples. Active tutorial sessions for engaged learning and continuous feedback on progress. Assignments and laboratory exercises that involve work with commercial programmable logic circuits. | |||||||||
| Teaching Method Delivery | Face-to-face | Teaching Method Delivery Notes | ||||||||
| WEEK | TOPIC | REFERENCE | ||||||||
| Week 1 | Introduction | R1: Ch1 | ||||||||
| Week 2 | Introduction, Digital Systems and Binary Numbers | R1: Ch1 | ||||||||
| Week 3 | Boolean Algebra and Logic Gates | R1: Ch2 | ||||||||
| Week 4 | Gate-Level Minimization | R1: Ch3 | ||||||||
| Week 5 | Gate-Level Minimization | R1: Ch3 | ||||||||
| Week 6 | Combinational Logic | R1: Ch4 | ||||||||
| Week 7 | Combinational Logic | R1: Ch4 | ||||||||
| Week 8 | MIDTERM EXAM | -- | ||||||||
| Week 9 | Combinational Logic | R1: Ch4 | ||||||||
| Week 10 | Synchronous Sequential Logic | R1: Ch5 | ||||||||
| Week 11 | Synchronous Sequential Logic | R1: Ch5 | ||||||||
| Week 12 | Synchronous Sequential Logic | R1: Ch5 | ||||||||
| Week 13 | Registers and Counters | R1: Ch6 | ||||||||
| Week 14 | Registers and Counters | R1: Ch6 | ||||||||
| Week 15 | General Revision | -- | ||||||||
| Assessment Methods and Criteria | Evaluation Tool | Quantity | Weight | Alignment with LOs | AI Usage |
| Final Exam | 1 | 35 | 1, 2, 4 | Not Allowed | |
| Semester Evaluation Components | |||||
| Laboratory/Simulation Assignments | 1 | 20 | 3, 5 | Not Allowed | |
| Quizzes | 2 | 20 | 1, 2, 4 | Not Allowed | |
| Midterm exam | 1 | 25 | 1, 2, 4 | Not Allowed | |
| *** ECTS Credit Calculation *** | |||||
| Activity | Hours | Weeks | Student Workload Hours | Activity | Hours | Weeks | Student Workload Hours | |||
| Lecture Hours | 3 | 14 | 42 | Assignments | 1 | 10 | 10 | |||
| Lab & Reporting | 2 | 10 | 20 | Home Study | 1 | 13 | 13 | |||
| In-term Exam Study | 15 | 1 | 15 | Final Exam Study | 15 | 2 | 30 | |||
| Project | 4 | 5 | 20 | |||||||
| Total Workload Hours = | 150 | |||||||||
| *T= Teaching, P= Practice | ECTS Credit = | 6 | ||||||||
| Course Academic Quality Assurance: Semester Student Survey | Last Update Date: 24/09/2025 | |||||||||