EE405 Software Engineering Project
EE405 Software Engineering Project
Syllabus | International University of Sarajevo - Last Update on Mar 03, 2026
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Electrical and Electronics Engineering
Nasser Badawi
Course Lecturer
Course Objectives
The main objective of this course is divided into two parts: 1) Theoretical Part: it aims to equip the students with an understanding of the R&D Software Engineering Process for real industrial applications according to the National/International Standardization. 2) Experimental Part: it includes the programming and the experimental test of different speed controllers for eDrives. System Control will be performed using one of following Processor Architectures: a) 32-Bit RISC-based Processor Architecture “NIOS II” using Altera FPGA Technology from Intel. b) 32-Bit Hybrid-based Processor Architecture using “AURIX TC299” from Infineon. Two Programming languages are required for the project, C-Embedded and FPGA-based VHDL programming
Learning Outcomes
After successful completion of the course, the student will be able to:
Course Materials
Required Textbook
The used FPGA manual, The used microcntroller manual, and other hardware and software datasheet needed
Additional Literature
--Teaching Methods
Class/Laboratory discussions
Team work project (Each Team has maximum 4 Students), supported by tutorial sessions for engaged learning and continuous feedback on progress
The project involves the implementation of a real digital processing system covering the several R&D phases including the technical analysis , documentation and presentation
Weekly Topics
| Week | Topic | Readings / References |
|---|---|---|
| 1 | Introduction, project plan | Notes |
| 2 | Documentation of project plan | Notes |
| 3 | C-Embbeded project work | Notes |
| 4 | C-Embbeded project work | Notes |
| 5 | C-Embbeded project work | Notes |
| 6 | C-Embbeded project work | Notes |
| 7 | C-Embbeded project work | Notes |
| 8 | Midterm exam | |
| 9 | FPGA project work | Notes |
| 10 | FPGA project work | Notes |
| 11 | FPGA project work | Notes |
| 12 | FPGA project work | Notes |
| 13 | FPGA project work | Notes |
| 14 | FPGA project work | Notes |
| 15 | QA | Notes |
Course Schedule (All Sections)
| Section | Type | Day 1 | Venue 1 | Day 2 | Venue 2 |
|---|---|---|---|---|---|
| EE405.1 | Course | - | - | - | - |
| EE405.1 | Tutorial | - | - | - | - |
Office Hours & Room
| Day | Time | Office | Notes |
|---|---|---|---|
| Friday | 11:00 - 12:00 |
Assessment Methods and Criteria
Assessment Components
Final Exam
AI: Not AllowedAlignment with Learning Outcomes :
Midterm_Theo_Part
AI: Not AllowedAlignment with Learning Outcomes :
Midterm_Prac_Part
AI: Not AllowedAlignment with Learning Outcomes :
Home_Work (Mid-Report)
AI: Not AllowedAlignment with Learning Outcomes :
IUS Grading System
| Grading Scale | IUS Grading System | IUS Coeff. | Letter (B&H) | Numerical (B&H) |
|---|---|---|---|---|
| 0 - 44 | F | 0 | F | 5 |
| 45 - 54 | E | 1 | ||
| 55 - 64 | C | 2 | E | 6 |
| 65 - 69 | C+ | 2.3 | D | 7 |
| 70 -74 | B- | 2.7 | ||
| 75 - 79 | B | 3 | C | 8 |
| 80 - 84 | B+ | 3.3 | ||
| 85 - 94 | A- | 3.7 | B | 9 |
| 95 - 100 | A | 4 | A | 10 |
Late Work Policy
Information about late submission policies will be shared during class and posted in this section. Please check back for official guidelines.
ECTS Credit Calculation
📚 Student Workload
This 6 ECTS credit course corresponds to 150 hours of total student workload, distributed as follows:
Lecture hours
30 hours ⏳ (15 week × 2 h)
Homeworks
20 hours ⏳ (10 week × 2 h)
Lab work
60 hours ⏳ (15 week × 4 h)
Mid-term exam study
20 hours ⏳ (2 week × 10 h)
Final exam study
20 hours ⏳ (2 week × 10 h)
150 Total Workload Hours
6 ECTS Credits
Course Policies
Academic Integrity
All work submitted must be your own. Plagiarism, cheating, or any form of academic dishonesty will result in disciplinary action according to university policies. When in doubt about citation practices, consult the instructor.
Attendance Policy
Students are expected to adhere to the attendance requirements as outlined in the International University of Sarajevo Study Rules and Regulations. Excessive absences, whether excused or unexcused, may impact academic performance and eligibility for assessment. Mandatory sessions (e.g., labs, workshops) require attendance unless formally exempted. For detailed policies on absences, documentation, and penalties, please refer to the official university regulations.
Technology & AI Policy
Laptops/tablets may be used for note-taking only during lectures. Phones should be silenced and put away during all class sessions. Audio/video recording requires prior permission from the instructor.
Artificial Intelligence (AI) Usage: The use of AI tools (e.g., ChatGPT, Copilot, Gemini) varies by assessment component. Please refer to the AI usage indicator next to each assessment item in the Assessment Methods and Criteria section above. Submitting AI-generated content as your own work, where AI is not explicitly allowed, constitutes an academic integrity violation.
Communication Policy
All course-related communication should occur through official university channels (institutional email or SIS). Emails should include [EE405] in the subject line.
Academic Quality Assurance Policy
Course Academic Quality Assurance is achieved through Semester Student Survey. At the end of each academic year, the institution of higher education is obliged to evaluate work of the academic staff, or the success of realization of the curricula.
Learning Tips
Be prepared to contribute thoughtfully during class discussions, labs, or collaborative work. Active participation deepens understanding and encourages critical thinking.
Complete assigned readings or prep materials before class. Take notes, highlight key ideas, and jot down questions. Aim to grasp core concepts and their applications—not just facts.
Use course frameworks or methodologies to analyze problems, case studies, or projects. Begin early to allow time for reflection and refinement. Seek feedback to improve your work.
Don’t hesitate to reach out when something is unclear. Use office hours, discussion boards, or peer networks to clarify concepts and stay on track.
Syllabus Last Updated on Mar 03, 2026 | International University of Sarajevo
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Referencing Curricula Print this page
| Course Code | Course Title | Weekly Hours* | ECTS | Weekly Class Schedule | ||||||
| T | P | |||||||||
| EE405 | Software Engineering Project | 2 | 4 | 6 | ||||||
| Prerequisite | EE325 | It is a prerequisite to | - | |||||||
| Lecturer | Nasser Badawi | Office Hours / Room / Phone | Friday: 11:00-12:00 |
|||||||
| nbadawi@ius.edu.ba | ||||||||||
| Assistant | Assistant E-mail | |||||||||
| Course Objectives | The main objective of this course is divided into two parts: 1) Theoretical Part: it aims to equip the students with an understanding of the R&D Software Engineering Process for real industrial applications according to the National/International Standardization. 2) Experimental Part: it includes the programming and the experimental test of different speed controllers for eDrives. System Control will be performed using one of following Processor Architectures: a) 32-Bit RISC-based Processor Architecture “NIOS II” using Altera FPGA Technology from Intel. b) 32-Bit Hybrid-based Processor Architecture using “AURIX TC299” from Infineon. Two Programming languages are required for the project, C-Embedded and FPGA-based VHDL programming |
|||||||||
| Textbook | The used FPGA manual, The used microcntroller manual, and other hardware and software datasheet needed | |||||||||
| Additional Literature |
|
|||||||||
| Learning Outcomes | After successful completion of the course, the student will be able to: | |||||||||
|
||||||||||
| Teaching Methods | Class/Laboratory discussions. Team work project (Each Team has maximum 4 Students), supported by tutorial sessions for engaged learning and continuous feedback on progress. The project involves the implementation of a real digital processing system covering the several R&D phases including the technical analysis , documentation and presentation. | |||||||||
| Teaching Method Delivery | Face-to-face | Teaching Method Delivery Notes | ||||||||
| WEEK | TOPIC | REFERENCE | ||||||||
| Week 1 | Introduction, project plan | Notes | ||||||||
| Week 2 | Documentation of project plan | Notes | ||||||||
| Week 3 | C-Embbeded project work | Notes | ||||||||
| Week 4 | C-Embbeded project work | Notes | ||||||||
| Week 5 | C-Embbeded project work | Notes | ||||||||
| Week 6 | C-Embbeded project work | Notes | ||||||||
| Week 7 | C-Embbeded project work | Notes | ||||||||
| Week 8 | Midterm exam | |||||||||
| Week 9 | FPGA project work | Notes | ||||||||
| Week 10 | FPGA project work | Notes | ||||||||
| Week 11 | FPGA project work | Notes | ||||||||
| Week 12 | FPGA project work | Notes | ||||||||
| Week 13 | FPGA project work | Notes | ||||||||
| Week 14 | FPGA project work | Notes | ||||||||
| Week 15 | QA | Notes | ||||||||
| Assessment Methods and Criteria | Evaluation Tool | Quantity | Weight | Alignment with LOs | AI Usage |
| Final Exam | 1 | 50 | Not Allowed | ||
| Semester Evaluation Components | |||||
| Midterm_Theo_Part | 1 | 20 | Not Allowed | ||
| Midterm_Prac_Part | 1 | 20 | Not Allowed | ||
| Home_Work (Mid-Report) | 1 | 10 | Not Allowed | ||
| *** ECTS Credit Calculation *** | |||||
| Activity | Hours | Weeks | Student Workload Hours | Activity | Hours | Weeks | Student Workload Hours | |||
| Lecture hours | 2 | 15 | 30 | Homeworks | 2 | 10 | 20 | |||
| Lab work | 4 | 15 | 60 | Mid-term exam study | 10 | 2 | 20 | |||
| Final exam study | 10 | 2 | 20 | |||||||
| Total Workload Hours = | 150 | |||||||||
| *T= Teaching, P= Practice | ECTS Credit = | 6 | ||||||||
| Course Academic Quality Assurance: Semester Student Survey | Last Update Date: 27/03/2026 | |||||||||