CS303 Digital Design

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Course Code Course Title Weekly Hours* ECTS Weekly Class Schedule
T P
CS303 Digital Design 3 2 6 Tuesday 11.00-12.50, Thursday 09.00-9.50
Prerequisite MATH101 It is a prerequisite to
Lecturer Office Hours / Room / Phone

Currently not available

E-mail
Assistant Sejla Dzakmic Assistant E-mail
Course Objectives To introduce the main building blocks of digital circuits and develop the skills of the students in the area of logic design and digital systems
Textbook Digital Design, Morris M. Mano, Michael D. Ciletti, Pearson (5th Ed.)
Learning Outcomes After successful  completion of the course, the student will be able to:
  1. Express, convert and calculate with real numbers having different bases
  2. Analyse and optimize digital system with respect to number and type of logical gates
  3. Design and test digital circuits, configured into functional systems in programmable devices using VHDL
  4. Understand architecture and timing diagrams of digital circuits that include memory blocks (RAM)
  5. Write a report that clearly and concisely explains the results obtained in laboratory exercises
Teaching Methods Class discussions with examples. Active tutorial sessions for engaged learning and continuous feedback on progress. Assigments and laboratory exercises that involve work with commercial programmable logic circuits.
WEEK TOPIC REFERENCE
Week 1 Introduction, Number systems, BCD, Grey code, logic gates, truth tables 1.1 - 1.6, 2.1 - 2.4
Week 2 Boolean algebra rules, Karnough-maps, logic gates, minterms, maxterms 2.5 - 2.8, 3.1 - 3.8
Week 3 Programmable devices - introduction to hardware definition language, HW1 3.9
Week 4 Multiplexers, Demultiplexers, Encoders, Decoders, Q1 4.9 - 4.12
Week 5 Adders 4.5, 4.6
Week 6 CMOS gates - internal structure. TTL and CMOS logic levels, fan-in/out, HW2 NOTES
Week 7 Transients, propagation delay, repetition before midterm, Q2 NOTES
Week 8 MIDTERM EXAM
Week 9 Flip-flops and latches 5.1 - 5.4
Week 10 Sequential circuits - state machines, HW3 5.5 - 5.6
Week 11 State machine analysis and design, Q3 5.7 - 5.8
Week 12 Timers, registers, memory 6.1 - 6.6
Week 13 Memory - RAM, HW4 7.1 - 7.3
Week 14 Memory - timing diagrams, ROM, LUT, Q4 7.5 - 7.8
Week 15 Revision
Assessment Methods and Criteria Evaluation Tool Quantity Weight Alignment with LOs
Final Exam 1 40
Semester Evaluation Compenents
Homeworks 3oo4 4 10
Quizes 3oo4 4 10
Midterm exam 1 19
Laboratory Assignments 3 21
***     ECTS Credit Calculation     ***
 Activity Hours Weeks Student Workload Hours Activity Hours Weeks Student Workload Hours
Lecture Hours 3 14 42 Home Study 2 14 28
Assignments 3 4 12 Assignments 3 4 12
Active Tutorials 2 8 16 Final Exam Study 16 1 16
Home Study 2 14 28 Home Study 2 14 28
        Total Workload Hours = 150
*T= Teaching, P= Practice ECTS Credit = 6
Course Academic Quality Assurance: Semester Student Survey Last Update Date: 04/03/2020
QR Code for https://ecampus.ius.edu.ba/course/math101-calculus-i

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