CS309 Advanced Logic Design

Syllabus | International University of Sarajevo - Last Update on Mar 03, 2026

Referencing Curricula

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Computer Sciences and Engineering

Academic Year

2025 - 2026

Semester

Spring

Course Code

CS309

Weekly Hours

3 Teaching + 2 Practice

ECTS

6

Prerequisites

Teaching Mode Delivery

Face-to-face

Prerequisite For

-

Teaching Mode Delivery Notes

-

Cycle

I Cycle

Prof. Jane Doe

Mohammad Al Samman

Course Lecturer

Position

Assistant Professor Dr.

Email

malsamman@ius.edu.ba

Phone

033 957 223

Assistant(s)

-

Assistant E-mail

Course Objectives

To enhance techniques and skills of students within the area of digital design, and develop the skills of building and documenting work on digital systems using project oriented approach.

Learning Outcomes

After successful completion of the course, the student will be able to:

1

Assemble and test digital systems configured into functional unit as combinational and sequential circuits on bread board and simulation program,

2

Explain the internal structure of PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Array),

3

Apply digital design techniques to implement different digital circuits in programmable devices using VHDL or Verilog,

4

Write a report that clearly and concisely explains the results obtained in laboratory exercises.

Course Materials

Required Textbook

Morris M. Mano, Michael D. Ciletti, Digital Design, Pearson (5th Ed.)

Additional Literature

Brown, Stephen, and Zvonko Vranesic. "Digital Logic with VHDL Design." McGRAW HILL company (2005).

Teaching Methods

Class discussions with examples

Active tutorial sessions for engaged learning and continuous feedback on progress

Special focus of laboratory exercises that involve work with commercial programmable logic circuits

Weekly Topics

This weekly planning is subject to change with advance notice.

Week	Topic	Readings / References
1	Course Syllabus & Mechanics. Review	Chapters 1-4
2	Review of Digital Design	Chapter 5
3	Registers and Counters	Chapter 6
4	Introduction to VHDL	Class Notes
5	Implementing combinational and sequential logic in VHDL	Class Notes
6	Memory and Programmable Logic	Chapter 7
7	Memory and Programmable Logic	Chapter 7
8	MIDTERM EXAM
9	Design at the Register Transfer Level	Chapter 8
10	Design at the Register Transfer Level	Chapter 8
11	Testing of Logic Circuits	Chapter 10
12	Testing of Logic Circuits	Chapter 10
13	Project Work	Class notes
14	Project Work	Class notes
15	Project presentation and Revision	Class notes

Course Schedule (All Sections)

Section	Type	Day 1	Venue 1	Day 2	Venue 2
CS309.1	Course	Monday 15:00 - 17:50	A F1.23	-	-
CS309.1	Tutorial	Monday 18:00 - 19:50	A F2.13	-	-

Office Hours & Room

Day	Time	Office	Notes
Tuesday	15:00 - 16:00	A F2.7
Wednesday	13:00 - 15:00	A F2.7
Thursday	11:00 - 13:00	A F2.7

Assessment Methods and Criteria

Assessment Components

30%x1

Final Exam

AI: Not Allowed

Alignment with Learning Outcomes : 1 2 3 4

20%x1

Project

AI: Not Allowed

Alignment with Learning Outcomes : 1 2 3 4

5%x1

Quiz

AI: Not Allowed

Alignment with Learning Outcomes : 1 2 3 4

20%x1

Midterm exam

AI: Not Allowed

Alignment with Learning Outcomes : 1 2 3 4

25%x6

Laboratory Reports

AI: Not Allowed

Alignment with Learning Outcomes : 1 2 3 4

IUS Grading System

Grading Scale	IUS Grading System	IUS Coeff.	Letter (B&H)	Numerical (B&H)
0 - 44	F	0	F	5
45 - 54	E	1	F	5
55 - 64	C	2	E	6
65 - 69	C+	2.3	D	7
70 -74	B-	2.7	D	7
75 - 79	B	3	C	8
80 - 84	B+	3.3	C	8
85 - 94	A-	3.7	B	9
95 - 100	A	4	A	10

Late Work Policy

Information about late submission policies will be shared during class and posted in this section. Please check back for official guidelines.

ECTS Credit Calculation

📚 Student Workload

This 6 ECTS credit course corresponds to 150 hours of total student workload, distributed as follows:

Lecture hours

33 hours ⏳ (11 week × 3 h)

In-term exam study

12 hours ⏳ (1 week × 12 h)

Home study

28 hours ⏳ (14 week × 2 h)

Final exam study

13 hours ⏳ (1 week × 13 h)

Active tutorials

28 hours ⏳ (14 week × 2 h)

Reporting

18 hours ⏳ (6 week × 3 h)

Project

18 hours ⏳ (3 week × 6 h)

150 Total Workload Hours

6 ECTS Credits

Course Policies

Academic Integrity

All work submitted must be your own. Plagiarism, cheating, or any form of academic dishonesty will result in disciplinary action according to university policies. When in doubt about citation practices, consult the instructor.

Attendance Policy

Students are expected to adhere to the attendance requirements as outlined in the International University of Sarajevo Study Rules and Regulations. Excessive absences, whether excused or unexcused, may impact academic performance and eligibility for assessment. Mandatory sessions (e.g., labs, workshops) require attendance unless formally exempted. For detailed policies on absences, documentation, and penalties, please refer to the official university regulations.

Technology & AI Policy

Laptops/tablets may be used for note-taking only during lectures. Phones should be silenced and put away during all class sessions. Audio/video recording requires prior permission from the instructor.

Artificial Intelligence (AI) Usage: The use of AI tools (e.g., ChatGPT, Copilot, Gemini) varies by assessment component. Please refer to the AI usage indicator next to each assessment item in the Assessment Methods and Criteria section above. Submitting AI-generated content as your own work, where AI is not explicitly allowed, constitutes an academic integrity violation.

Communication Policy

All course-related communication should occur through official university channels (institutional email or SIS). Emails should include [CS309] in the subject line.

Academic Quality Assurance Policy

Course Academic Quality Assurance is achieved through Semester Student Survey. At the end of each academic year, the institution of higher education is obliged to evaluate work of the academic staff, or the success of realization of the curricula.

Learning Tips

Engage Actively

Be prepared to contribute thoughtfully during class discussions, labs, or collaborative work. Active participation deepens understanding and encourages critical thinking.

Read and Review Purposefully

Complete assigned readings or prep materials before class. Take notes, highlight key ideas, and jot down questions. Aim to grasp core concepts and their applications—not just facts.

Think Critically in Assignments

Use course frameworks or methodologies to analyze problems, case studies, or projects. Begin early to allow time for reflection and refinement. Seek feedback to improve your work.

Ask Questions Early

Don’t hesitate to reach out when something is unclear. Use office hours, discussion boards, or peer networks to clarify concepts and stay on track.

Syllabus Last Updated on Mar 03, 2026 | International University of Sarajevo

Referencing Curricula Print this page

Course Code	Course Title					Weekly Hours*		ECTS		Weekly Class Schedule
						T	P
CS309	Advanced Logic Design					3	2	6		Mon. 15:00 to 17:50
Prerequisite	CS303				It is a prerequisite to	-
Lecturer	Mohammad Al Samman				Office Hours / Room / Phone	Tuesday: 15:00-16:00 Wednesday: 13:00-15:00 Thursday: 11:00-13:00 A F2.7 - 033 957 223
E-mail	malsamman@ius.edu.ba
Assistant					Assistant E-mail
Course Objectives	To enhance techniques and skills of students within the area of digital design, and develop the skills of building and documenting work on digital systems using project oriented approach.
Textbook	Morris M. Mano, Michael D. Ciletti, Digital Design, Pearson (5th Ed.)
Additional Literature	Brown, Stephen, and Zvonko Vranesic. "Digital Logic with VHDL Design." McGRAW HILL company (2005).
Learning Outcomes	After successful completion of the course, the student will be able to:
	Assemble and test digital systems configured into functional unit as combinational and sequential circuits on bread board and simulation program, Explain the internal structure of PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Array), Apply digital design techniques to implement different digital circuits in programmable devices using VHDL or Verilog, Write a report that clearly and concisely explains the results obtained in laboratory exercises.
Teaching Methods	Class discussions with examples. Active tutorial sessions for engaged learning and continuous feedback on progress. Special focus of laboratory exercises that involve work with commercial programmable logic circuits.
Teaching Method Delivery	Face-to-face			Teaching Method Delivery Notes
WEEK	TOPIC								REFERENCE
Week 1	Course Syllabus & Mechanics. Review								Chapters 1-4
Week 2	Review of Digital Design								Chapter 5
Week 3	Registers and Counters								Chapter 6
Week 4	Introduction to VHDL								Class Notes
Week 5	Implementing combinational and sequential logic in VHDL								Class Notes
Week 6	Memory and Programmable Logic								Chapter 7
Week 7	Memory and Programmable Logic								Chapter 7
Week 8	MIDTERM EXAM
Week 9	Design at the Register Transfer Level								Chapter 8
Week 10	Design at the Register Transfer Level								Chapter 8
Week 11	Testing of Logic Circuits								Chapter 10
Week 12	Testing of Logic Circuits								Chapter 10
Week 13	Project Work								Class notes
Week 14	Project Work								Class notes
Week 15	Project presentation and Revision								Class notes

Assessment Methods and Criteria	Evaluation Tool	Quantity	Weight	Alignment with LOs	AI Usage
	Final Exam	1	30	1,2,3,4	Not Allowed
	Semester Evaluation Components
	Project	1	20	1,2,3,4	Not Allowed
	Quiz	1	5	1,2,3,4	Not Allowed
	Midterm exam	1	20	1,2,3,4	Not Allowed
	Laboratory Reports	6	25	1,2,3,4	Not Allowed
* ECTS Credit Calculation *

Activity	Hours	Weeks	Student Workload Hours	Activity				Hours	Weeks	Student Workload Hours
Lecture hours	3	11	33	In-term exam study				12	1	12
Home study	2	14	28	Final exam study				13	1	13
Active tutorials	2	14	28	Reporting				3	6	18
Project	6	3	18
				Total Workload Hours =						150
*T= Teaching, P= Practice				ECTS Credit =						6
Course Academic Quality Assurance: Semester Student Survey									Last Update Date: 05/03/2026

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